Timing of and minimising external influences on digital signals

ABSTRACT

The performance of digital signals depends to a great extent on the frequency. However, the higher the frequency, the shorter the remaining time, in which digital signals can be reliably received by a receiver from a driver via a printed conductor. The run time of the clock pulse and signals must be optimized in such a way that no timing losses occur at any location, even in the extreme environmental conditions. The invention improves the timing and minimizes external influences by coupling the output signals to an internal PLL clock pulse.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is the U.S. National Stage of InternationalApplication No. PCT/EP02/09693, filed Aug. 30, 2002 and claims thebenefit thereof. The International Application claims the benefits ofEuropean application No. 01121403.8 EP filed Sep. 6 2001, both of theapplications are incorporated by reference herein in their entirety.

FIELD OF INVENTION

[0002] The invention relates generally to improving the timing andminimizing external influences on digital signals and by coupling theoutput signals to an internal PLL clock pulse.

BACKGROUND OF THE INVENTION

[0003] The performance of digital systems is heavily dependent on thefrequency. On the other hand, the higher the frequency, the shorter isthe time remaining to convey digital signals reliably from a driver viaa conductor track to the receivers. Limiting factors are theclock-to-output time, the run time on the board, the setup/hold time ofthe receiver, output and input skew (skew of the transmitters andreceivers) and clock skew or jitter (tskew).

[0004]FIG. 1 shows the timing of a digital signal at the output of thedriver of a transmitter and at the input of the receiver, the diagramillustrating the time effect of the factors mentioned.

[0005] The setup time requirement determines for how many ns before theclock edge a signal to be clocked in has to be stable. The hold timerequirement determines for how long after a clock edge the signal has toremain stable. Thus, if the position of the times of clock and signalwith respect to each other is varied, this has a positive effect inrespect of one requirement, but a negative effect in respect of theother requirement.

[0006] In extremely favorable environmental conditions (low temperature,high supply voltage, powerful drivers, receiver with small parasiticcapacity) the signals are very fast. In this case a hold time problemarises.

[0007] In extremely unfavorable environmental conditions (hightemperature, low supply voltage, weak drivers, receiver with largeparasitic capacity) the signals are very slow. However, the clock maynot also be slow. In this case a setup time problem arises.

[0008] The run time of clock and signals must be optimized in such a waythat even in extreme environmental conditions no timing violations ariseanywhere. The tradeoff determines the maximum possible frequency andtherefore the performance of the system or imposes constraints in thearchitecture.

[0009] Typically, a table is produced which lists all the timingparameters to be taken into account for each signal and calculates abudget or a violation. This is performed for the fast and the slow case.The parameters can be influenced (within limits) via the choice ofcomponents, the board layout and (if transmitter or receiver arecontained in an ASIC) via the ASIC design. The limits result from thecomponents chosen (driver strength, setup/hold time according to thedata sheet), the distances between the components on the board, thearchitecture of the networks (unidirectional/bidirectional signals,number of drivers/receivers involved) and frequency or clock period.Then an optimization is performed. However, if the optimization isperformed for the slow case, this is detrimental to the fast case, andvice versa. TABLE 1 Setup and hold time margin calculation signal tskewtco, tco, trun, trun, tsetup thold hold setup name chip min max min maxmargin mar- gin

[0010] In some cases the problem was also not even solved at all, butworked around. An example is SDRAM address signals in the PC: In thiscase the address signals are sent off from the driver and clocked in atthe receiver only with the next-but-one clock. This has implications forthe design of the SDRAM controller and the performance of the overallsystem. Moreover, PC motherboards running at an SDRAM bus frequency of133 MHz are now only equipped with a maximum of 3 SDRAM modules (DIMMs)in order to steer clear of timing problems. However, this limits themaximum possible memory configuration.

[0011] An already partly common variant for minimizing the clock skewbetween transmitter and receiver uses a PLL in the transmitter device(e.g. ASIC); see FIG. 2. In this arrangement, clock and signals for theSDRAMs come from the same chip. An additional clock output is loopedback again to the PLL of the transmitter and in fact has the samephysical length as the receiver clock. The PLL transmits this feedbackclock earlier in line with the board run time t_run so that in this waythe feedback clock will then arrive in phase with the reference clockclk_ref at the PLL input of the ASIC. Because the receiver clock has thesame run time, the receiver clock is also automatically in phase at itsreceiver at time T0. The clock skew between transmitter and receiver istherefore always equal to zero.

SUMMARY OF THE INVENTION

[0012] The invention leads to an approximately constant clock-to-outputtime for the slow and the fast case. By means of board layout measuresit is also ensured that the edge distance of clock and signals on theboard is maintained and is unchanged at the receiver. In this way it ispossible to increase the maximum frequency or to operate the busfrequency with fewer restrictions. The design risk for the timing isconsiderably reduced (in FIG. 3 arrows indicate that all signal andclock ranges are implemented identically, i.e. including the linelengths and the buffers which determine the clock-to-output time. Theclock-to-output times are therefore independent of environmentalinfluences and also of the ASIC fabrication process. The run times ofthe signals on the board are also set to equality and are thereforeindependent of environmental influences.

[0013] An important feature of the invention is that the output FFs forthis bus are not to be clocked using the normal system clock for theASIC core, but with a clock which is derived from the output clock ofthe PLL (see FIG. 3). This clock is in fact sent off correspondinglysomewhat earlier by the PLL in the slow case, in order to be in phasewith the reference clock at the PLL input. In the slow case the outputsof the signals are also weaker and need longer on the board. For thisreason it is useful to send the signals off earlier too. This takesplace automatically through retiming by means of the output clock. Inthe fast case, clock and signals are sent off correspondingly later.Buffer type and placing of clock and signal output buffers areimplemented in identical fashion. The clock-to-output distance tco isalways the same in both extreme cases. The clock-to-output time can bereduced even further by means of delay elements in the output clockpath.

[0014] In the board layout the run times of the signals are also set toequality with those of the clocks and feedback clocks. All the signalsof the bus are trimmed to the same length. The clock-to-signal distancefrom the driver device to the receivers therefore remains the same,irrespective of the environmental conditions. In this way the number ofparameters is immediately reduced in the timing table: clock-to-output,output skew and run time skew. Measures are also taken to ensureequality of the parameters for the fast or slow case.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1. shows the timing of a digital signal at the output at theoutput of the driver of a transmitter and at the input of the receiver,

[0016]FIG. 2. shows an already partly common variant for minimizing theclock skew between transmitter and receiver uses a PLL in thetransmitter device,

[0017]FIG. 3. shows a clock which is derived from the output clock ofthe PLL, and

[0018]FIG. 4. shows an SDRAM memory controller comprising an ASIC, 4+512MB SDRAM DIMMs and a clock multiplier for 133 MHz.

DETAILED DESCRIPTION OF INVENTION

[0019] The principle presented is realized by way of example in an SDRAMmemory controller comprising an ASIC, 4+512 MB SDRAM DIMMs and a clockmultiplier for 133 MHz (see FIG. 4).

[0020] The PLL ensures that at time T0 the rising clock edges are inphase without skew both at the ASIC and also at the DIMMs. The signalsare also sent off using the same clock, relative to the clock outputwith tco. If the run times of clock and signals are set to equality inthe layout, then the distance between clock and signals is alwaysexactly still Tco. This applies regardless of whether environmentalfactors and ASIC process factors have an accelerating or deceleratingeffect. Inaccuracies arise due to run time differences, output skew,board skew, DIMM skew and DIMM clock skew and must be taken into accountin the conventional way.

[0021] In this exemplary embodiment, a PLL clock driver and three delaylines can also be seen. Furthermore, the input signals are handledseparately. These delay lines are used to describe the independentadjustability of the timing of the forward and reverse direction ofbidirectional digital signals.

[0022] By using the invention as described it is possible, in spite ofthe special requirements not yet applicable in the PC environment (4DIMM slots with angled sockets due to low board form factor height of 3cm; address signals apply only one clock), to realize a bus clock rateof 133 MHz with reliable timing and without performance penalties forthe system.

[0023] Finally there follows an exemplary explanation with regard to thenecessary distance between clock and signal for transmitter andreceiver:

[0024] a) assumption: transmitter and receiver receive in-phase clocksfrom an external source. The transmitter has a specific clock-to-outputtime tco. The receiver requests a specific hold time thd (after theclock edge the signal must be kept stable for a certain time thd stillso that the logic level is reliably detected).

[0025] b) simplest solution if tco>thd: Even if no run time at all werepresent on the board, the hold time would nevertheless be complied with.

[0026] c) If tco<thd: The board run time ensures a delay in the signal,thus ensuring that the hold time is still complied with.

[0027] d) The board run time is very long (great distance) and the clockperiod very short (high frequency): The board run time delays the signaledge so much that the setup time tsu of the receiver is not compliedwith. The signal is then possibly sampled with the past logic level!

[0028] This case would be normal for 133 MHz and 10 cm distance andlarge capacitive load with a plurality of receivers. For this reason thesignals are coupled to the clock with tco and both are sent offtogether. Because of the equal lengths on the board the distance tco tothe receiver is maintained and there conforms to the hold time as in b).The SPLL ensures that clocking out is performed by precisely as muchleading as required.

[0029] e) In the implementation it was even shown that tco<thd.

[0030] This can be shifted to the correct setting by means of the boardPLL and delay 1 (see FIG. 4).

[0031] Abbreviations Used

[0032] DIMM: Dual Inline Memory Module

[0033] DRAM: Dynamic Random Access Memory

[0034] SDRAM: Synchronous Dynamic Random Access Memory

[0035] DDR SDRAM: Double Data Rate Synchronous Random Access Memory

[0036] PLL: Phase Locked Loop

[0037] SPLL: PLL for SDRAM

[0038] Skew: Angled position, distortion

[0039] Clock skew: Time difference arising due to run times of differentlengths and/or due to different driver strengths or receiver loads.Clock skew causes some receiver registers to switch earlier/later thanothers.

[0040] Output skew: The dispersion range of the tco times with relatedsignals of the same type (buses)

[0041] Input skew: The dispersion range of the input run times from theexternal pin to the receiver in the chip with buses

1. A digital system, comprising: a processing device for processing datawhich is clocked via a first clock signal; a data output register fortransmitting data over a signal line to a further digital system and aPLL device which generates a second clock signal from the first clocksignal, the second clock signal is supplied as a clock signal to thefurther digital system via a clock line; and a feedback loop of the PLLdevice having a same run time as the signal line, wherein the secondclock signal is supplied as a clock signal to the data output register,the clock line has the same run time as the said signal line.
 2. Thedigital system according to claim 1, wherein the run times within thedigital system and a buffer types of clock signals and data signals arekept identical.
 3. The digital system according to claim 1, whereinequality of the run times is achieved by dimensioning the physicallength of the respective lines and/or a delay device.
 4. The digitalsystem according to claim 2, wherein equality of the run times isachieved by dimensioning the physical length of the respective linesand/or a delay device.